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NXP Semiconductors /QN908XC /FSP /FIR_CFG_CH5

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Interpret as FIR_CFG_CH5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FIR_CH5_COEF_BASE0FIR_CH5_TAP_LEN 0 (FIR_CH5_BUF_CLR)FIR_CH5_BUF_CLR

Description

FIR channel 5 configuration register

Fields

FIR_CH5_COEF_BASE

FIR channel 5 coefficient base address
FIR_CH5_TAP_LEN

FIR channel 5 tap length
FIR_CH5_BUF_CLR

FIR channel 5 buffer clear

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data